1. Field of the Invention
The present invention relates to input-output devices and in particular to the protection of components of cascoded input-output devices which interface between two voltage domains.
2. Description of the Prior Art
It is known to provide input-output devices which transform a signal in one voltage domain into a signal in another voltage domain. For example, in the SOC (system-on-chip) context, whilst on-chip components may operate in a lower voltage domain, it is often desirable for these components to be able to pass signals off-chip, where such signals may be defined in a higher voltage domain. This may for example be due to a given communication protocol to which the signals should adhere.
Whilst techniques are known for providing such functionality, difficulties arise with the trend for on-chip components to become ever smaller. With state of the art CMOS technologies, both core and I/O (input-output) device power supplies have moved to lower voltages in order to reach the contemporary speed and power consumption levels required. In parallel, transistor dimensions and oxide thicknesses have also decreased.
For example, in 45 nm technologies, the “standard” external power is now 1.8V (where it was 3.3V or 2.5V at previous technology scales). To be able to reach the high frequencies demanded of these 1.8V devices, the oxide thickness has decreased to around 28 to 32 Å (where it was previously around 50 Å).
However, in order to be compatible with older devices and some existing standard protocols, it is desirable for input-output devices to be able to operate at a higher voltage than their nominal voltage (e.g. an I/O device operating at 1.8V nominal voltage domain being able to interface with a 3.3V voltage domain).
Such an arrangement can be problematic, due to the potential for I/O components in the 1.8V voltage domain to be exposed to excessive voltage differences, potentially overstressing those components. This overstress can lead to reduced component lifetimes due such phenomena as oxide breakdown and hot carrier injection (HCI).
In particular, in the example of such I/O devices which interface between two voltage domains, problems can arise during switching events (i.e. when the input signal transitions, thus causing the output signal to transition) when transient stress on components can easily arise. These problems are particularly problematic in the output buffer of the I/O device, since a large off-chip load may be being driven, meaning that these stressful transient events can occur for a non-negligible period of time.
Furthermore, in the context of these ever-smaller technology scales, it is typically a key requirement that power consumption should be kept as low as possible, meaning that it is highly desirable for the DC power consumption of such devices to be kept as low as possible.
FIG. 1 schematically illustrates the output buffer 10 of such an I/O device, wherein the output voltage supplied to PAD 20 (for connection to an off-chip device) is configured to range between 0V and 3.3V (GND to DVDD). In order to provide this output range with I/O components configured to operate in a lower voltage range (in this example in a range of 1.8V), the output buffer driver switches (PFET 30 and NFET 60) are each cascoded with an output buffer cascode switch (PFET 40 and NFET 50). In the arrangement illustrated, the I/O device inverts the output signal with respect to the input signal. The gates of each output buffer cascode switch is tied to 1.8V. The output buffer can thus be seen itself to be divided into an upper voltage domain (generally denoted 70) and a lower voltage domain (generally denoted 80), the upper voltage domain ranging from 1.8V to 3.3V and the lower voltage domain ranging from 0V to 1.8V.
This arrangement of the output buffer 10 provides reliable performance in DC situations, but the cascode switches 40 and 50 can suffer from VDS (voltage drain-source) overstress during transients. In other words, when the input signal (divided by a level shifter (not illustrated) to form the inputs into driver switches 30 and 60) transitions, causing the output voltage to transition on PAD 20, the drain-source voltage across each of these transistors can exceed their tolerances. For example, in the situation where the PAD voltage transitions from high to low (3.3V to 0V), the PFET 30 is switched off (by the rising transition of the input signal). At the same time, NFET 60 switches on and begins to lower the voltage at the intermediate point int-N between the NFETs 50 and 60. However, the PAD voltage only starts to fall once NFET 50 has sufficient gate-source voltage (VGS) to sink the current. This means that by the time the PAD voltage starts to fall, int-N is already so low that it creates some VDS stress (potentially leading to HCI damage—also known as hot carrier degradation) on NFET 50. The same effect can also affect PFET 40 on a rising transition of the PAD voltage, due to the voltage at the intermediate point int-P beginning to rise before PFET 40 has sufficient VGS to sink the current.
FIG. 2 illustrates a simulation of the potential VDS stress that could be caused to an NFET transistor such as cascode switch 50 in FIG. 1, in the case where the PAD voltage VPAD makes a high to low transition. It can be seen that the voltage at int-N Vint-N falls sharply, causing a spike in the VDS of the cascode transistor, before its VGS is sufficient for the cascade transistor to turn on. In particular, it can be seen that the VDS of NFET 50 peaks at around 3.05V, stressing this component which operates at 1.8V nominal voltage. The current in the NFETs INFET is also shown.
Whilst increasing the gate length could go some way to reducing this effect, such techniques are insufficient to adequately counteract this problem. Alternatively a triple cascode output buffer could be provided, yet this would result in an undesirably large I/O device.
Accordingly, it would be desirable to provide an improved technique which enabled input-output devices to provide a power-efficient interface between voltage domains, without the components of those input-output devices that are designed to operate in a lower voltage domain being stressed by exposure to excessive voltage differences resulting from the interface to a higher voltage domain.